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Lead ASIC/FPGA Development and Verification Engineer

Company: Boeing
Location: Garden Grove
Posted on: February 12, 2020

Job Description:

At Boeing, we are all innovators on a mission to connect, protect, explore and inspire. From the sea bed to outer space, you'll learn and grow, contributing to work that shapes the world. Find your future with us. Position Overview:Boeing Defense Space & Security seeks a Lead Digital ASIC/FPGA Design and Verification Engineer to support the Satellite Capabilities organization and multiple satellite product lines based in El Segundo, CA.Position Responsibilities:

  • Utilize high-level architectural documentation along with algorithm description and implement DSP functions for functions such as decimation, interpolation, general filtering, up-down conversion, digital beamforming, and channelization.
  • Develop mathematical models in SystemVerilog to verify design implementation and develop and run scripts and Make files.
  • Leads analysis of customer and system requirements and development of architectural approaches and detailed specifications for various electronic products.
  • Leads development of high-level and detailed designs consistent with requirements and specifications.
  • Leads reviews of testing and analysis activity to assure compliance to requirements.
  • Identifies, tracks and statuses technical performance measures to measure progress and ensure compliance with requirements.
  • Leads activities in support of Supplier Management with make/buy recommendations and other technical services.
  • Coordinates engineering support throughout the lifecycle of the product.
  • Plans research projects to develop concepts for future product designs to meet projected requirements.
  • Works under minimal directionThis position offers relocation based on candidate eligibility. Basic relocation is available for internal candidates.Basic Qualifications (Required Skills/Experience): -
    • This position must meet Export Control compliance requirements, therefore a "US Person" as defined by 22 C.F.R. - 120.15 is required. "US Person" includes US Citizen, lawful permanent resident, refugee, or asylee.
    • Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
    • 5 -or more years" of experience in Digital ASIC/FPGA design or verification.
    • Work experience simulating a digital design using SystemVerilog Assertions.Preferred Qualifications (Desired Skills/Experience):
      • Experience leading development of architectural approaches from customer and system requirements.
      • Experience designing digital ASIC/FPGA architectural design documents (micro-architecture documents with timing diagrams, detailed design blocks, etc.).
      • Experience deriving digital ASIC/FPGA requirements specification from higher-level (system or board-level) requirements specifications.
      • Experience identifying, tracking, and providing status of technical performance metrics to measure progress and ensure compliance with requirements.
      • Experience leading a team of engineers.
      • Experience developing complex and high data rate designs.
      • Work experience performing RTL synthesis.
      • Work experience performing clock cross domain analysis (CDC).
      • Work experience performing Static Timing Analysis and correcting timing violations.
      • Work experience writing Universal Verification Methodology (UVM) sequences and virtual sequences.
      • Bachelor's degree and 12 or more years' experience in digital ASIC/FPGA design and verification, Master's degree with 10 or more years' experience in digital design/verification, or PhD degree with 7 years of experience in digital design/verification.
      • Work experience using Linux or Unix terminal commands.
      • Experience using scripting languages: Make, Perl, Python, shell scripts, etc.
      • Experience using Revision Control Systems: Subversion (SVN), CVS, Git.
      • Work experience using Object Oriented Programming concepts: Inheritance, Polymorphism, etc.
      • Work experience using Universal Verification Methodology (UVM): Experience creating drivers, monitors, predictors, and scoreboards.
      • Work experience creating a self-checking simulation testbench from scratch.Typical Education / ExperienceDegree and typical experience in engineering classification: Bachelor's and 9 or more years' experience, Master's with 7 or more years' experience or PhD with 4 or more years' experience. Bachelor, Master or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry. ABET is the preferred, although not required, accreditation standard.Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies. -

Keywords: Boeing, Garden Grove , Lead ASIC/FPGA Development and Verification Engineer, Other , Garden Grove, California

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