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Integrated Circuit Layout Engineer

Company: Boeing
Location: Garden Grove
Posted on: January 15, 2020

Job Description:

At Boeing, we are all innovators on a mission to connect, protect, explore and inspire. From the seabed to outer space, you'll learn and grow, contributing to work that shapes the world. Find your future with us. @Boeing, we create the future - of mobility, autonomy, speed, endurance, space access and exploration, undersea vehicles, cybersecurity, communication and much, much more. - We connect people, products and ideas around the world. - We protect people and nations. - We explore the mysteries of the universe from seabed to space to cyberspace. - We inspire future generations of innovators, dreamers and doers.We are Boeing Research & Technology (BR&T): Boeing's global research and development team creating and implementing innovative technologies that make the impossible possible and enabling the future of aerospace. - We are engineers and technicians, skilled scientists and bold innovators; Join us and put your passion, determination, and skill to work building the future! - - #TheFutureIsBuiltHere - #ChangeTheWorldWithin BR&T, Boeing's Solid State Electronics Development organization (SSED) performs microelectronics technology development and design for aerospace systems.We develop digital, analog, and RF Systems on Chip (SoCs) for radar, navigation, electronic warfare, communications, processing, and other electronic systems. These systems are used on Boeing airborne, terrestrial, and satellite platforms. Designs are implemented with state of the art semiconductor process technologies including CMOS, GaAs, GaN, and SiGe. SSED uses external wafer fabrication but performs design (architecture, RTL, synthesis, circuits, physical design, verification, packaging and test) in house. - SSED has numerous microelectronics projects, funded both by internal Boeing customers and external Government Science and Technology (S&T) customers. SSED's large staff of microelectronics engineers conduct research and designs microelectronics hardware in support of these projects.We are seeking experienced integrated circuit (IC) layout engineers to implement custom analog/mixed-signal circuits in state-of-the-art CMOS (---22nm) and SiGe semiconductor fabrication processes. The qualified candidate will have experience performing custom IC layout to achieve tight matching, high speed, low noise, and low power consumption. Circuits for custom layout may include analog or digital standard cells, resistors and capacitors, IO cells, ESD structures, and SRAM leaf cells.Tasks/responsibilities include:

  • Working closely with IC / chip design team on block-level and chip-level floor-planning
  • Performing cell-level layout, block-level layout, and chip assembly
  • Performing physical verification including design rule checks (DRC), layout vs. schematic (LVS) checks, and electrical rule checks (ERC)
  • Perform / support parasitic extraction (PEX) and analysis
  • Drive continued improvement of layout practices and procedures
  • Positions available in: Huntington Beach, CA - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Tukwila, WA (positions in Tukwila WA are union represented positions)Positions Available for: Level 3, level 4, level 5Basic Qualifications (Required Skills/Experience):
    • Ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship
    • Bachelor's, Master's or Doctorate of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics or chemistry
    • 5+ years of experience in full-custom analog/mixed-signal IC layout
    • Experience exercising and debugging the IC verification flowPreferred Qualifications (Desired Skills/Experience):
      • Experience with performance analog and high-power layout techniques
      • Experience with industry-standard electronic design automation (EDA) tools for IC layout and physical verification - e.g. those from Cadence, Mentor Graphics, and Synopsys
      • Experience with standard cell development and/or familiarity with structured, pitched, or arrayed layout
      • Experience with performance analog and high-power layout techniques
      • Experience with Radiation-Hardened By Design (RHBD) layout techniques
      • Experience with scripting to automate IC layout (e.g. SKILL, Perl, Python)
      • Experience with experimental process technologies (e.g. Gate-all-around FETs (GAAFETs))
      • Active US Security clearanceTypical Education/Experience: - Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 5 or more years' related work experience or an equivalent combination of technical education and experience (e.g. PhD, Master+3 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.Relocation: This position offers relocation based on candidate eligibilityDrug Free Workplace: Boeing -is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies.Union: Positions available in Tukwila WA are union represented positionsEmployee Referral: Referral to this job is eligible for bonusAdditional Information: All information provided will be checked and may be verified.Please apply as soon as possible for this role as recruitment may commence before the end date.Experience Level
        Individual Contributor
        Contingent Upon Program Award
        No, this position is not contingent upon program award

Keywords: Boeing, Garden Grove , Integrated Circuit Layout Engineer, Other , Garden Grove, California

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